Design and simulation of low-power ADC using double-tail comparator
نویسندگان
چکیده
---------------------------------------------------------------------***--------------------------------------------------------------------Abstract Double-tail comparator is basically designed for SAR-ADC in order to optimize the power with which the circuit operates on high-speed. The circuit is designed under 90 nm CMOS technology means by reducing the technology the parameters get also reduced. The designing of double-tail comparator is based on conventional dynamic comparator and also the circuit is modified by applying the adiabatic logic circuit to the double-tail comparator which is the lowpower circuit. The power performance results are obtained are improved with the help of adiabatic logic and systematically sizing the transistors of the comparators. Since, the comparator operates on lowpower, gives fast speed even in low supply voltages. Similarly, this designing of double-tail comparator is placed between SAR-ADC to optimize the power performance of the circuit and then the ADC circuit reduces the power and operates faster.
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